Event Details
Watch the webinar recording here: Watch Now
About I3C Protocol:
MIPI Alliance introduced the I3C protocol in January 2017, and industries have adopted it rapidly ever since. Over the last 4 to 5 years, the I3C interface has been adopted for mobile, automotive, IoT, wearable, DDR5, and many more applications. As a result, I3C is becoming the default interface in many SOCs and devices. As technology moves towards the growth path, the demand for robust testing solutions has emerged at every stage of I3C implementation, including emulation and prototyping, post-silicon validation, and system-level deployment.
Who should Attend :
Design Engineers, Test Engineers, Post Silicon Validation engineers, System design engineers, Engineering managers, Application Engineers, SoC Emulation engineers, RTL Engineers, Firmware Engineers, Hardware Engineers, etc
Webinar Agenda:
In the webinar, you will learn about MIPI I3C protocol overview, Electrical validation, and Protocol analysis to support the growing needs of the market. This webinar is for all the engineers working on Silicon implementation, emulation, prototyping, Pre-silicon, post-silicon validation, and hardware and firmware development. This webinar will help you debug complex engineering designs and develop reliable systems.
- I3C Protocol Basics
- Overview of I3C Protocol
- Pain points and challenges of the I3C Protocol Analysis
- I3C Tester with capabilities to generate I3C packets and Conformance Test Suite
- Electrical Validation
- I3C decoding using a low-cost logic analyzer
- Live product demo
Speakers
Mr. Godfree Coelho, Founder & CEO
Mr. Chandrala Brijesh
Godfree Coelho has a total experience of 25+ years in the test and measurement Industry. He worked for Tektronix/HP/Agilent Technologies in his initial 15 years of career. Godfree worked as a product manager and sales of test and measurement equipment. He has successfully defined a product roadmap for power measurement solutions in Tektronix, launched initial power measurement software, and successfully planned and executed a go-to-market strategy.
Chandrala Brijesh is a Sr. Technical Lead with experience in Architecture, multi Clock Domain designs, and High-speed Protocols. He has deep expertise in high-speed memory protocols like UFS as well as the latest protocols like MIPI I3C. Brijesh is a B.E.graduate of VTU University and has done Post Graduation in VLSI and Embedded Systems from Pune University.
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