Protocol Analyzer
PCIe Low Power Side Band Signal Analyzer
Model No: PGY-PCIeLP-SBA
The PGY-PCIeLP-SBA PCIe Low Power Side Band Signal Analyzer that measures sideband signals timing measurements and reports failure during the low power entry and exist time over long period of time enabling test engineers test and debug the M.2 SSD devices over different operation conditions.
PGY-PCIeLP-SBA monitors CLKREQ, REFCLK, PERSET and PWR signals of the M.2 interface during the different operating conditions. It provides timing measurement of these signals as per PCIe and M.2 interface specification documents. User can also set hardware-based trigger on specific timing measurement failure and get notified during the long duration automated test environment. User interface displays timing diagram with abstract view of the 100MHz Ref Clk condition, the low power state, restart, power recycle and power on state of the during while running the test cases.
- PCIe
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Free Online Technical Support
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Free Software Updates
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Global Sales Support
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Evaluation Units Available
- Key Features
- Specifications
- Technical Library
- Low-Cost Logic Analyzer with continuous streaming capability to monitor sideband signals
- Plots the timing waveforms of PWR, CLKREQ, PERSET and REFCLK
- Power-ON State
- Restart
- Low power entry and exit from and to L0 State
- Measures timing parameters
- Reports timing parameter failure
- Trigger on Timing parameter failure
- Low Latency report support to overwrite T-CRON parameter
- Report Generation
| TCRH OFF | CLQREQ# de-asserted high to clock parked |
| TCRL ON | CLQREQ# asserted low to clock active |
| TPVGL | Power Valid to PERST# input active |
| TPERST#CLK | REFCLK stable before PERST# deassertion |
| TPERST | Assertion time of PERST# |
PGY-PCIeLP-SBA has M.2 extender board with access to all side band signals which can be connected to PCIe Low Power Side Band Signal Analyzer. The software runs in windows PC enables the configuration of Analyzer for measurements and trigger conditions. It continuously plots the timing waveforms and updates timing measurements summary statistical and detail information.
Configuration Panel
Configuration allows the users to easily select the timing parameters to be measured and set the trigger on any of this timing parameter failure. User can decide the duration of the capture in time (it can be few hours) or manually can stop the analysis. Pre and post trigger selection gives the option to view the data around the trigger condition.
Result Panel
The applicable timing measurements for each event is measured and displayed in the software along with timing waveforms. The timing plot display PWR, CLKREQ, PERSET and REFCLK. The REFCLK is plotted at abstract layer, whenever it changes the state to 100MHz as displayed as high state and off state is displayed in low state. The acquisition duration is limited by the user need. The acquired data is continuously streamed to host computer storage system.
Debug Panel
PGY-PCIeLP-SBA provides powerful debugging capabilities to user to see failure in the acquired data by following capabilities:
- Links the specific measurement to timing waveform using Markers
- Sorting the specific measurement to view all hits
- Sort the failed or pass measurements
- Latency Tolerance Report support
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