Analyzer
PCIe Protocol Analyzer
Model No: PGY-PCIeGen3/4/5
The PGY-PCIeGen3/4/5 -PA is a PCIe Protocol Analyzer that supports protocol analysis up to PCIe Gen5 speeds. PCIe design and test engineers can easily captures and record traces at 2.5, 5.0, 8, 16 and 32GT/s at specific event and obtain error report instantaneously at affordable price. This enables the design and test engineers to reduce the development time and address the time to market needs. PCIe data is captured using interposers between the root complex and end point (Device under test). PCIe Gen3/4/5 Protocol Analyzer’s software provides complete decode and error analysis of Transaction Layer Packets (TLPs), Data Link Layer Packets (DLLPs) and with LTSSM information.
- PCIe
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Free Online Technical Support
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Free Software Updates
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Global Sales Support
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Evaluation Units Available
- Key Features
- Specifications
- Technical Library
- PCIe Gen1/2/3/4/5-X4/8 Protocol Decode and Analysis.
- Currently supports four/eight lane PCIeGen1/2/3/4/5 Bus.
- M2/U.2/CEM/E1.S/SD Express interposer for speeds up to PCIe Gen5 is standard offering with protocol analyzer.
- NVME Protocol Decode Capabilities
- Optional solder down probe tips for four lanes for speeds up to PCIe Gen3 (8Gbps)
- Protocol Decoding of TS1, TS2, TLP, DLLP Packets.
- Hardware based protocol packet (TS1, TS2 and IDLE) filter capabilities.
- Software based search, filter-in and filter-out capabilities.
- Hardware based protocol aware trigger capabilities based on TS1, TS2, TLP and DLLP packet contents.
- Advanced multi-level if-then-else if trigger capabilities.
- Standard buffer size of 16GB and expandable to 64GB combined for TX and RX.
- Detailed view of each TLP/DLLP with all field values.
- LTSSM Analysis for PCIe protocol traffic.
- Memory segmentation with each segment with different trigger condition
- Trigger out signal at trigger event allows the triggering of other instruments such as an oscilloscope.
- Interface to host system using USB 3.0.
- Decoded data packets can be exported to .txt file for further analysis.
- PGY Protocol Analyzer is light weight and can be deployed for on-site/ field tests.
- Field upgradeable to enable easy maintenance and remote firmware upgrade to latest feature set.
1. Will be supported in our future release
| Data Rates Supported | PCIe Gen1, Gen2, Gen 3, Gen 4, Gen5 |
| Link Width | Four/Eight lanes (Four/Eight TX and Four/Eight RX). |
| Probes | M.2 Interposer (Standard), Optional orderable CEM, U.2, E1.S, SD Express Interposers Solder Down Active Probes for speeds up to PCIe Gen3. (Optional) |
| Protocol Decode | TS1, TS2, TLP, DLLP, SDS, IDLE, EIOS, EIEOS, FTS, SKP, NVME, Decoding of Configuration register |
| Trace Capture Size | Supports Continuous streaming of Protocol data to Host computer SSD/HDD and Post Capture up to buffer size. |
| Trigger | Based on TS1, TS2, TLP, DLLP. |
| Connectors | Interposer Interface and Trigger in/out signal |
| Interface for Host Computer | USB 3.0 |
| Host Computer Requirements | Processor: Intel i7 10th Generation or better (Equivalent) Operating System: Windows 8.0/8.1/10/11 64bit OS. RAM: minimum 16GB but the product would give a faster response for 32GB/64GB/more. Storage: 256GB SSD or more (minimum storage capacity of 1GB should be available in the hard disk drive. User can use more storage based on trace storage requirement.) Display resolution: 1024X768. Interface: Host computer should support USB 3.0 interface. |
| Dimension (WxHxD) | (W x H x D) (20.5X5X25) cms. (Tentative) |
| Weight | Approx. 6 kg |
| Power Requirement | 12V, 6A DC Power Supply (AC/DC Supplied along with Analyzer). |
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