PCIe Low Power Side Band Signal Analyzer Data Sheet

The PGY-PCIeLP-SBA PCIe Low Power Side Band Signal Analyzer that measures sideband signals timing measurements and reports failure during the low power entry and exist time over long period of time enabling test engineers test and debug the M.2 SSD devices over different operation conditions.

PGY-PCIeLP-SBA monitors CLKREQ, REFCLK, PERSET and PWR signals of the M.2 interface during the different operating conditions. It provides timing measurement of these signals as per PCIe and M.2 interface specification documents. User can also set hardware-based trigger on specific timing measurement failure and get notified during the long duration automated test environment. User interface displays timing diagram with abstract view of the 100MHz Ref Clk condition, the low power state, restart, power recycle and power on state of the during while running the test cases.